Accepted yosys 0.5.0+20151013gitf13e387-2~exp1 (source) into experimental
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Hash: SHA512
Format: 1.8
Date: Sun, 21 Feb 2016 12:21:37 +0100
Source: yosys
Binary: yosys
Architecture: source
Version: 0.5.0+20151013gitf13e387-2~exp1
Distribution: experimental
Urgency: low
Maintainer: Debian Science Maintainers <debian-science-maintainers@lists.alioth.debian.org>
Changed-By: Ruben Undheim <ruben.undheim@gmail.com>
Description:
yosys - Framework for Verilog RTL synthesis
Changes:
yosys (0.5.0+20151013gitf13e387-2~exp1) experimental; urgency=low
.
* Added autopkg test for synthesis for iCE FPGA.
* Updated standards to 3.9.7 - no needed changes
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